1

Combinatorial equivalence of (0, 1) circulant matrices

Year:
1969
Language:
english
File:
PDF, 599 KB
english, 1969
2

The Borel-Tanner Distribution

Year:
1960
File:
PDF, 652 KB
1960
3

A Knowledge-Based System for Designing Testable VLSI Chips

Year:
1985
Language:
english
File:
PDF, 14.50 MB
english, 1985
7

Digital Systems Testing and Testable Design || Fault Modeling

Year:
1994
Language:
english
File:
PDF, 3.30 MB
english, 1994
8

The formulation of some allocation and connection problems as integer programs

Year:
1966
Language:
english
File:
PDF, 626 KB
english, 1966
9

An unexpected result in coding the vertices of a graph

Year:
1967
Language:
english
File:
PDF, 736 KB
english, 1967
11

An optimal scheduling algorithm for testing interconnect using boundary scan

Year:
1991
Language:
english
File:
PDF, 1.07 MB
english, 1991
13

Test program synthesis for modules and chips having boundary scan

Year:
1993
Language:
english
File:
PDF, 1.91 MB
english, 1993
15

Partial scan design of register-transfer level circuits

Year:
1995
Language:
english
File:
PDF, 2.12 MB
english, 1995
16

Estimation of BIST Resources During High-Level Synthesis

Year:
1998
Language:
english
File:
PDF, 377 KB
english, 1998
18

An IEEE 1149.1 Compliant Test Control Architecture

Year:
1998
Language:
english
File:
PDF, 170 KB
english, 1998
19

TA-PSV—Timing Analysis for Partially Specified Vectors

Year:
2002
Language:
english
File:
PDF, 355 KB
english, 2002
21

Self-diagnosis of regular arrays of processors

Year:
1992
Language:
english
File:
PDF, 874 KB
english, 1992
22

A Note on Three-Valued Logic Simulation

Year:
1972
Language:
english
File:
PDF, 535 KB
english, 1972
24

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Year:
1984
Language:
english
File:
PDF, 1.69 MB
english, 1984
25

Implementation of Threshold Nets by Integer Linear Programming

Year:
1965
Language:
english
File:
PDF, 586 KB
english, 1965
26

Generation of optimal code for expressions via factorization

Year:
1969
Language:
english
File:
PDF, 804 KB
english, 1969
38

A methodology for custom VLSI layout

Year:
1983
Language:
english
File:
PDF, 1.43 MB
english, 1983